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[ELanguage] xilinx_primitives

Description: verilog code for alu
Platform: | Size: 47104 | Author: manish kumar | Hits:

[VHDL-FPGA-Verilog] alu_32_bit

Description: 一个Verilog语言写的３２位ＡＬＵ的源码。-A language written in Verilog source code for a 32-bit ALU.
Platform: | Size: 2048 | Author: sunny | Hits:

[VHDL-FPGA-Verilog] alu

Description: alu for verilog it s simple
Platform: | Size: 1024 | Author: JunKim | Hits:

[VHDL-FPGA-Verilog] processor

Description: verilog program for alu
Platform: | Size: 8192 | Author: saiprasanth | Hits:

[VHDL-FPGA-Verilog] ALUALUcontrol

Description: 实现32位的ALU，使其能够支持基本的指令。用Verilog HDL语言或VHDL语言来编写，实现ALU及ALU控制器。 -To achieve 32-bit ALU, so that it can support the basic directives. With the Verilog HDL language or VHDL language to write, implement ALU and the ALU controller.
Platform: | Size: 1060864 | Author: 于伟 | Hits:

[VHDL-FPGA-Verilog] 4

Description: simple code based on verilog shifter , cla ,clg , ALU , PC
Platform: | Size: 3072 | Author: Tera | Hits:

[VHDL-FPGA-Verilog] 5

Description: simple code based on verilog shifter , cla ,clg , ALU ,PC, decoder , tb_top
Platform: | Size: 16384 | Author: Tera | Hits:

[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24

Description: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器 在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Platform: | Size: 4946944 | Author: 石 | Hits:

[VHDL-FPGA-Verilog] 74181ALU

Description: alu功能。实现计算机的数字运算。运用的是74181芯片-alu function. The number of computer-based operations. Use the 74181 chip. .
Platform: | Size: 1024 | Author: 刘墉 | Hits:

[VHDL-FPGA-Verilog] alu

Description: this is source code in verilog for arithmatic logic unit for RISC cpu
Platform: | Size: 63488 | Author: Harshit B J | Hits:

[VHDL-FPGA-Verilog] alu2

Description: verilog alu 8bit for engineers
Platform: | Size: 91136 | Author: pedram | Hits:

[VHDL-FPGA-Verilog] pipelALU

Description: pipeline ALU verilog code
Platform: | Size: 2048 | Author: holyhi | Hits:

[VHDL-FPGA-Verilog] rtl_v

Description: 8051 alu in verilog not vhdl this fucking shit website
Platform: | Size: 106496 | Author: dark schneider | Hits:

[VHDL-FPGA-Verilog] alu

Description: 用verilog写的alu的简单的功能，包括移位，加减法-With the alu verilog write simple functions, including shift, addition and subtraction, etc.
Platform: | Size: 40960 | Author: alex | Hits:

[VHDL-FPGA-Verilog] alu

Description: Verilog,PIC系列ALU设计，加法、减法、逻辑运算，二进制调整-Verilog,PIC ALU Design ADD SUB XOR AND
Platform: | Size: 1024 | Author: yueweijie | Hits:

[VHDL-FPGA-Verilog] ALU

Description: ALU 与ALU控制器 实验 VHDL Verilog 语言设计-ALU VHDL Verilog
Platform: | Size: 1024 | Author: abc | Hits:

[Other] alu

Description: 一个简单的算术逻辑运算模块的Verilog代码，可进行加、减、自增、自减，比较大小等运算-alu module
Platform: | Size: 1024 | Author: Dora Yu | Hits:

[VHDL-FPGA-Verilog] alu

Description: It is 32 bit ALU code in Verilog HDL programming Language
Platform: | Size: 1024 | Author: srikanth | Hits:

[Software Engineering] ALU

Description: 计算机ALU的verilog设计，能够实现加减与或运算-Computer ALU verilog design can add and subtract with or computing
Platform: | Size: 2048 | Author: hello | Hits:

[Other] ALU

Description: MIPS ALU written using Verilog HDL. Computer structure project
Platform: | Size: 3072 | Author: viet | Hits:
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